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DS26504DK
FPGA ID Registers
BID: BOARD ID (Offset = 0x0000)
BID is read only with a value of 0xD.
XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset = 0x0002)
XBIDH is read only with a value of 0x0.
XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset = 0x0003)
XBIDM is read only with a value of 0x1.
XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset = 0x0004)
XBIDL is read only with a value of 0x6.
BREV: BOARD FAB REVISION (Offset = 0x0005).
BREV is read only and displays the current fab revision.
AREV: BOARD ASSEMBLY REVISION (Offset = 0x0006)
AREV is read only and displays the current assembly revision.
PREV: PLD REVISION (Offset = 0x0007)
PREV is read only and displays the current PLD firmware revision.
FPGA Status Registers
Register Name: BUSMO
Register Description: DS26504 Bus Mode
Register Offset: 0x0011
Bit #
Name
Default
7
LevCPOL
—
6
LevCPHA
—
5
HW
—
4
SPI
—
3
INMUX
—
2
IMUX
—
1
MNMUX
—
0
MMUX
—
The FPGA derives values in the BUSMO register from the levels present at the DS26504 pins.
Bit 7: LevCPOL. When set the DS26504 CPOL pin is high. Note: This pin is called A3/CPOL/L1 in
parallel/serial/hardware modes.
Bit 6: LevCPHA. When set the DS26504 CPHA pin is high. Note: This pin is called A2/CPHA/L0 in
parallel/serial/hardware modes.
Bit 5: HW. When set the DS26504 is in hardware mode.
Bit 4: SPI. When set the DS26504 is in SPI (3-wire) mode.
Bit 3: INMUX. When set the DS26504 is in Intel nonmultiplexed mode.
Bit 2: IMUX. When set the DS26504 is in Intel multiplexed mode.
Bit 1: MNMUX. When set the DS26504 is in Motorola nonmultiplexed mode.
Bit 0: MMUX. When set the DS26504 is in Motorola multiplexed mode.
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相关代理商/技术参数
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DS26504LN
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DS26504LN+T&R
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